1. Field of the Invention
This invention relates to Read Only Memory (ROM) manufacturing techniques and more particularly to code implanting during ROM manufacturing.
2. Description of Related Art
ROM devices are standard components of modern computer systems. A ROM comprises an array of Metal Oxide Semiconductor Field Effect Transistor (MOSFET's) arranged in columns and rows, wherein predetermined MOSFET's are either permanently conductive or nonconductive as a function of the variety of transistor. The alternative on/off operation of these devices states of the MOSFETs is adapted to use for storage of data, which remains in the device when the external power supply is off.
A ROM device includes an array of parallel, closely spaced lines comprising regions formed of a heavily doped impurity in a semiconductor substrate having an opposite type of background impurity. On the surface of the substrate an insulating layer is formed. Another array of closely spaced conductive lines formed on the surface of the insulating layer is arranged at right angles to the spaced lines in the substrate. Insulating layers are formed on the upper array of conductive lines. A metallurgy layer connects the two arrays of lines to circuits to address the lines and to read the data stored in the RAM, as is well known in the art.
At the intersection of a conductive line in the upper array which is commonly referred to as a "word line" and a pair of adjacent lines in the substrate, known as the "bit lines", a MOSFET is formed. The spaced lines in the substrate comprise the source and drain for the MOSFET. The conductive word line serves as the gate electrode of the MOSFET. Certain predetermined MOSFETs can be made permanently conductive by forming a region of an impurity of the opposite type from that in the bit lines, between adjacent bit lines and beneath the corresponding conductive line. This permanently non-conductive region is known as a code implant, and it is placed in the substrate to provide specific binary data. Such a ROM is constructed of NAND circuits as contrasted with the NOR type circuits employed in connection with this invention.
The conventional manufacturing process is to form the code implant regions very early in the ROM fabrication process, since an annealing step is required to activate the implanted impurity and also to recrystallize any implanted areas of the substrate. The annealing process involves heating the substrate above an acceptable temperature, which would damage the completed device, since the aluminum metallization conventionally used is damaged above a temperature of about 400.degree. C. to about 450.degree. C. for more than a minimum time interval, and the maximum possible temperature is the melting point of aluminum which is about 660.degree. C.
FIG. 1A shows an early stage of a prior art process for forming a ROM commences with a N- doped semiconductor substrate 10 upon which a P-well 12 is formed by doping with an opposite (P-) type of dopant followed by forming buried N+ bit lines (not shown in FIG. 1A.) Above the P-well 12 is formed a silicon dioxide gate oxide layer 14 about 200 .ANG. thick. Above the gate oxide layer 14, word lines 15 are formed from a layer of polysilicon 16 followed by a layer of a refractory silicide (polycide) 18, each about 1,500 .ANG. thick. Adjacent to the word lines 15 are formed silicon dioxide spacers 20. The refractory silicide is selected from silicides of refractory metals such as Ta, W, Ti and Mo.
In FIG. 1B, the prior art process continues with application of a layer of photoresist 22 which is patterned to form openings 21 therein for application of boron B.sup.11 dopant ions 23 to be implanted between adjacent buried N+ bit lines (not shown) and beneath the polysilicon word lines 15 with an ion implanter operating at an energy level of about 180 keV.
In FIG. 1C, the prior art process continues with formation of a layer 24 of USG (Undoped Silicon Glass) by APCVD (Atmospheric-Pressure Chemical Vapor Deposition) to a thickness of about 1,500 .ANG..
In FIG. 1D, the next step of the prior art process is to deposit a BPSG layer 26 to a thickness of about 7200 .ANG. with boron (B) about 3.0% and phosphorous (P) about 4.6%. The process used in the prior art to deposit the BPSG layer 26 also comprises APCVD.
In FIG. 1E, the prior art device of FIG. 1D has been heated to reflow the BPSG layer 26 at a temperature of about 900.degree. C. which reflow the BPSG layer 26, thereby planarizing the USG layer 24 and BPSG layer 26 with a combined thickness remaining at about 8700 .ANG..
In FIG. 1F, after the device of FIG. 1E has been subjected to formation of contacts by photolithography and is coated with a metal layer 28. A process of photolithography and etching is involved. The metal is deposited first by evaporation or preferably by sputtering. Photoresist is then applied, masked and developed to form the pattern desired.
Next in the prior art process, there is passivation and pad etching followed by formation of the alloy by annealing at 410.degree. C. in a furnace.
The conventional mask ROM programming methods include: programming by field oxide, channel ion implant, etc. It is desirable for a mask ROM that small die size, coincides with short turn around time. However, it is difficult when a conventional process, such as one of the above mentioned methods, is used for the process to achieve a short turn around time. This invention uses existing facilities in an industrial laboratory to achieve the short turn around time goal in an industrial factory.
In Hong et al "Very Late Programming Process for Mask ROM" (Ser. No. 08/044,936) a process of ROM manufacture includes buried bit lines, covered by a thin gate oxide layer on which polysilicon word lines are formed which are covered with a thick film of BPSG between 3,000 .ANG. A and 8,000 .ANG. thick. Metallization is applied formed of aluminum, a refractory metal, refractory metal silicide or heavily doped polysilicon. The refractory metal or the refractory metal silicide are stated to be preferred because they will withstand higher temperatures than aluminum and can be annealed at 850.degree. C. for about 15 minutes or 900.degree. C. for 5 minutes. A resist layer is applied and patterned to define a code implant pattern. The code implantation is performed preferably with boron B.sup.11 ions at a power of about 180 keV with an implantation dosage of about 1 E 13 to 1 E 14 atoms/cm.sup.2. After implantation of the ions they are activated. Preferably, a passivating layer of silicon dioxide or silicon nitride in the range of 5,000 .ANG. to 10,000 .ANG. thick is deposited by PECVD. When the metallization is aluminum with a thick barrier metal layer, the activation of the implanted ions and recrystallization "must be done by rapid thermal annealing (RTA). In the critical RTA process . . . the device must be heated to a temperature not greater than about 650.degree. C., but above a temperature of 550.degree. C. and maintained for a time in the range between 3 and 10 minutes. The atmosphere of the RTA process may be an inert gas such as nitrogen."
Applicants find that it is difficult to employ an implant energy of 180 keV to implant through a thickness of 3,000 .ANG. or particularly through a structure comprising a 9,000 .ANG. thick combination of BPSG and a polycide word line. Accordingly an object of this invention is to use a thinner layer of BPSG with a thickness less than about 3,000 .ANG..
The double charge method has a very low throughput, which is not well adapted to mass production.
The late programming etch back method is not adapted to a practical application from the point of end point issues and it is more complicated than desired. Accordingly an object of this invention is to avoid the late programming etch back method.
An object of this invention is to employ a lower temperature annealing process to achieve a high throughput.
Another object of this invention is an improved narrow metal pattern processing technique.
A further object of this invention is to employ an improved thinner BPSG layer.